Feasible Operating Boundary Extraction for MW‐Class SiC Inverters in High‐Speed Drives

ABSTRACT

Advances in wide‐bandgap (WBG) semiconductors now enable inverter designs capable of operating at higher speeds, higher voltages, and significantly greater power levels. Operating at high fundamental and switching frequencies enables improved power density, reduced current and voltage distortion, and enhanced overall drive efficiency. However, their practical extension to low‐voltage megawatt‐class systems is constrained by device paralleling, semiconductor losses, thermal management, current distortion, and implementation complexity. This paper presents a PLECS‐based electrothermal feasibility framework for extracting feasible operating boundaries of MW‐class SiC inverters for high‐speed drives. The main objective is to identify the maximum feasible switching frequency and engineering applicability limits of different topology, device, DC‐link, and modulation‐technique combinations under simultaneous constraints of efficiency, semiconductor junction temperature, and output‐current total harmonic distortion (THD). Two‐level, T‐type neutral‐point‐clamped (T‐NPC), and active neutral‐point‐clamped (ANPC) inverter topologies are evaluated using commercially available SiC discrete MOSFETs and power modules at 800 V and 1500 V DC‐link levels. The study evaluates switching and conduction losses, total harmonic distortion (THD), efficiency, and junction temperature across varying frequencies and modulation strategies, including space vector pulse‐width modulation (SVPWM) and discontinuous pulse‐width modulation (DPWM) variants. Suitable feasible solutions achieving efficiency, THD , and balanced cost–thermal trade‐offs are presented. A 25 kW SiC inverter prototype is used to validate the PLECS electrothermal model and support the predicted loss, efficiency, and temperature trends.