FASP: A Fault-Aware Hardware/Software Partitioning Framework for Security Verification in Reliable Digital Microfluidic Biochips

The existing computer-aided design approaches for Digital Microfluidic Biochips focus on optimising execution time and electrode utilisation, but overlook security verification overhead as a synthesis constraint. The advanced detection method, based on ResNet-50 deep neural networks with 98% accuracy, requires three to four orders of magnitude more computational capacity (3.8 GFLOPS) than the embedded biochip controllers. Existing reactive recovery approaches suffer from prohibitive latency, with re-synthesis algorithms requiring seconds to 33 minutes on desktop processors, causing timing violations incompatible with real-time bioassay constraints. We present a security-aware computer-aided design framework, called FASP (Fault-Aware Synthesis and Partitioning), that integrates the computational cost of verification as a design-time synthesis constraint through hardware and software partitioning to enable effective placement of the detection method. The formulation of a multi-objective optimisation problem for security integration across diverse computing substrates is presented, along with a synthesis algorithm with O ( k · r · n log  n ) complexity. The algorithm performs critical path analysis, selective module replication, and communication fabric synthesis to adapt the verification pipeline configuration to meet real-time deadlines and reliability requirements before deployment. Experimental results show this method yields an average verification success rate of 84.44% (over 5.59% better than the nearest baseline placements) across system scales from 4 to 324. The proposed method achieves synthesis times of 16–50 ms on average for redundancy levels 3–6, while an overall average latency of 128.86 ms enables the integration of verification directly into the design-time phase.