Exceptionally Matched p-SiNW/n-IGZO Complementary Field-Effect Transistors for Monolithic 3D Logic

Abstract

Monolithic three-dimensional (M3D) complementary field-effect transistors (CFETs) provide a route toward a higher logic density by vertically stacking complementary devices within the same footprint. Their realization through heterogeneous integration requires p- and n-channel transistors that are both individually high-performing and electrically matched. Here, we demonstrate high-performance heterogeneous Si/oxide M3D CFETs by vertically integrating p-type silicon nanowire (p-SiNW) FETs with n-type indium gallium zinc oxide (n-IGZO) transistors. The site-controlled p-SiNWs are formed through a scalable in-plane solid–liquid–solid (IPSLS) process without postgrowth hydrogen passivation, facilitating subsequent oxide–semiconductor integration. The vertically integrated p- and n-channel devices exhibit closely matched current-driving capabilities, near-zero threshold voltages, and subthreshold swings of 120 and 133 mV dec–1, respectively. This exceptional p/n matching enables sharp and well-balanced switching, yielding a peak voltage gain of 103 V/V at VDD = 5 V, a normalized gain of 20.6 V–1, and large, nearly symmetric noise margins (NML = 0.45 VDD and NMH = 0.44 VDD). The architecture is further extended to NOR, NAND, and OR gates with experimentally verified logic operations. These results establish a high-performance heterogeneous Si/oxide integration platform for dense and robust M3D complementary logic.