Engineering Interfacial Conduction in ALD‐Al ₂ O _x /STO Bilayer Dielectrics Toward Reliable Gate

ABSTRACT

Combining dielectrics with complementary properties is a widely used strategy for overcoming the trade‐off between achieving a high dielectric response and suppressing leakage current. Freestanding ultrathin SrTiO ₃ (FS‐STO), owing to its ultrahigh dielectric constant, is a promising component for bilayer gate stacks when integrated with large‐bandgap Al ₂ O _x . However, electrically active interfaces can emerge in such heterostructures between nominally insulating dielectric layers, introducing parasitic conduction and electrical instability during transistor operation. In this work, we systematically investigate how the dielectric–dielectric interface‐formation route influences the electrical behavior of Al ₂ O _x /STO bilayer dielectrics. Heterostructures formed by direct atomic layer deposition (ALD) of Al ₂ O _x onto STO exhibit a conductive region confined to a finite near‐interfacial depth on the STO side. Closed‐loop electrical measurements further reveal pronounced bias‐history‐dependent conductance, indicating the involvement of a slowly evolving interfacial charge state in addition to any static interfacial carrier contribution. In contrast, mechanically assembled Al ₂ O _x /FS‐STO stacks strongly suppress this conductive response while retaining the expected dielectric behavior of the bilayer oxide stack, with the Al ₂ O _x layer providing effective leakage suppression and improved electrical robustness. Monolayer MoS ₂ field‐effect transistors (FETs) incorporating a 5 nm Al ₂ O _x /40 u.c. FS‐STO dielectric exhibit a subthreshold swing as low as 85 mV dec ⁻¹ and an effective interfacial trap density of , comparable to devices based on single‐layer dielectrics. These results identify the interface formation route as an important design parameter for multilayer gate dielectrics and demonstrate mechanical assembly as a controlled strategy for suppressing parasitic interfacial conduction.