Enabling Next Generation Packaging with Glass Core Substrates: Material, TGV and Metallization Requirements

The increasing performance demands of artificial intelligence (AI), high-performance computing (HPC), and data center systems continue to drive the need for more advanced packaging solutions. Traditional organic laminate substrates, while cost-efficient and widely established, face growing limitations in dimensional stability, coefficient of thermal expansion (CTE) mismatch, and electrical performance when scaled to larger formats and higher I/O densities. These challenges have placed glass core substrates at the forefront of discussions as a next-generation material platform for advanced packaging.

Glass offers a compelling set of intrinsic advantages. With a CTE close to that of silicon, glass substrates reduce thermomechanical stress and warpage compared to organics. Their high dimensional stability and surface planarity support fine-line lithography and multilayer redistribution layers (RDLs). In addition, excellent dielectric properties enable lower signal loss and reduced crosstalk in high-frequency applications, while transparency opens the possibility of integrating optical interconnects. Together, these attributes position glass as a strong candidate for enabling heterogeneous integration and advanced system architectures.

To realize this potential, however, several stringent requirements must be addressed. Material selection is critical: homogeneity, low defect density, and mechanical robustness are prerequisites for yield and reliability. Thickness uniformity across large substrates becomes particularly important as the industry moves toward panel-level formats, where dimensions of up to 510 × 515 mm are envisioned.

Substrate size and scalability introduce further challenges. While wafer-level glass substrates (up to 300 mm) are suitable for early prototyping and adoption within existing toolsets, large-area panels are essential for cost-efficient high-volume manufacturing. This transition introduces process uniformity issues, new handling requirements, and supply chain adaptations that must be resolved for successful industrialization.

Most critically, the integration of through-glass vias (TGVs) defines the functional capability of glass substrates. TGVs transform glass from a passive carrier into an active interconnect platform. Meeting industry targets for small via diameters (<30 µm), high aspect ratios (up to 20:1), and dense via arrays requires advanced drilling technologies capable of precise positioning while minimizing microcracks and defects. These challenges extend beyond via formation to issues of alignment with silicon dies, pitch matching, and reliability under thermal cycling.

Equally demanding is the metallization of TGVs, which must provide conformal copper coverage along via walls and surfaces without voids or seams. The uniformity of deposition is crucial for ensuring electrical performance and long-term reliability. As dimensions scale downward, metallization approaches face growing complexity, requiring trade-offs between throughput, cost, and performance. Beyond copper, future requirements may include barrier and seed layers, Ni/Au finishes, or solder bump integration to support hybrid bonding and multi-layer interconnects.

Beyond materials and process technologies, the ecosystem perspective remains essential. Wafer-level formats enable adoption using existing semiconductor equipment, but panel-level glass substrates demand new process standards, handling concepts, and collaboration across the supply chain. Equipment vendors, material suppliers, and device manufacturers must jointly address these challenges to position glass as a practical and scalable solution.

This contribution will provide a comprehensive overview of the requirements and challenges associated with glass core substrates for advanced packaging. Emphasis will be placed on the critical role of TGVs, including formation, metallization, and reliability considerations, while situating these within the broader framework of material requirements, substrate dimensions, and wafer-to-panel transition. By highlighting both opportunities and hurdles, this work aims to foster scientific and technical discussion on how glass can enable the next generation of high-performance packaging for AI and HPC systems.