Electromigration Study of μPILR™ Platform for Fine-Pitch Flip chip Interconnects

Flip chip packaging technology is typically used for high-performance devices that require the interconnects to have the capability to carry high currents at elevated temperatures for extended periods of time. The current values can be as high as many hundreds of mili Amperes, which translates to more than 10,000 A/cm2. Increasing number of I/O per die and shrinking form factor has been in greater number and smaller size of the first level flip chip interconnections. This increases current density and translates to higher current crowding on both the die and substrate sides of the interconnects. In recent years this trend has been a driving factor for raising awareness of electromigration related failure for design and development of high-end flip chip interconnections. There are different solutions being implemented in the industry to address this concern, such as changing the UBM structure, adding barrier layers, changing the composition of solder, etc.

In this paper, the μPILR interconnect is investigated for flip chip electromigration characteristics. The μPILR platform is implemented by use of Cu bumps on substrate to facilitate first level flip chip interconnections.

Two μPILR flip chip interconnect designs are discussed in this study. For the package-level testing of the first design, a test vehicle was built with a die size of 18 mm x 20 mm x 0.75 mm, which was packaged on a substrate

measuring 40 mm x 40 mm x 1.24 mm. The package has more than 10,000 μPILR based interconnects with a minimum pitch of 0.150mm, and a maximum pitch of 0.2mm pitch. The chip has 0.105 mm diameter Sn/2.5Ag

solder bumps attached to it. The μPILR interconnects are present over the substrate pads with a solder mask opening of 0.090mm. 1000 hours of test results are discussed for three current levels of 0.5 A, 1 A and 1.5 A corresponding to current densities of 1.5 x 104 A/cm2, 3.0 x 104 A/cm2 and 4.5 x 104 A/cm2 respectively. Temperatures for these tests are kept at 120º C, 130º C and 150º C respectively. The result shows failure mechanism of electromigration void growth near die UBM whereas no substrate side void growth is observed. Next a modification in the μPILR flip chip joint design is discussed which involves Cu bump fabricated on a flip chip substrate by a controlled Cu-Cu joining process using Sn. Electromigration test results are presented for a simple Cu-Sn-Cu test structure that mimics a modified part of the interconnect structure representing 30 μm diameter Cu bump on substrate. These tests done at 160º C for current density of 7x 104 A/cm2 show no void growth for 1000 hours of current stressing and not more

than 3 % increase of initial test structure resistance.

In conclusion, a flip chip interconnect structure is investigated for its electromigration performance with fine pitch. Experimental results show more than 995 hours of lifetime at a current value of 1.5 A (4.5 x 104 A/cm2 ) and chip temperature of 150 0C for the 0.15mm pitch μPILR flip chip package.