Electrical Proxy-Based Defect Analysis of High-Volume Manufacturing (HVM) IGZO TFTs for Process Optimization

Abstract

Defect states critically determine the reliability of oxide thin-film transistors (TFTs), yet identifying the dominant degradation mechanism in high-volume manufacturing (HVM) environments remains challenging. Here, we decouple bulk defect and channel-coupled near-interface traps contributions in self-aligned top-gate IGZO TFTs fabricated on a Gen-6 production line using electrical proxy indicators derived from frequency-dependent C−V and low-frequency noise (LFN) measurements. The two indicators capture distributed defect states and channel-coupled traps with distinct physical sensitivities. The resulting defect phase diagram reveals that even when bulk defect density is minimized, significant degradation persists in the presence of high channel-coupled near-interface trap density, highlighting the critical role of interface-related traps in device stability. The electrical indicators reproduce depth-dependent defect distributions independently verified by XPS, enabling practical access to buried channel-coupled near-interface states without destructive chemical analysis. This work provides a practical, data-driven pathway for defect-aware process control in large-scale oxide electronics.