Effect of Silicon BEOL Presence on Solder Fatigue Life During Board-Level Thermal Cycling of WLCSP

Traditional electronics packaging qualification includes a board-level reliability (BLR) component, which is intended to simulate the customer system-level environment and characterize package-to-PCB interconnect integrity. BLR is a particularly critical stage of qualification for wafer-level chip-scale packaging (WLCSP) due to the sensitivity of interconnect performance to package size, and the limitations of ubiquitous materials used in WLCSP manufacturing. In the context of mobile electronics, perhaps the most challenging BLR stress to accommodate is thermal cycling (TC) during which the large mismatch in thermal expansion between the package and PCB causes an accumulation of plastic deformation within the interconnects (in most cases a lead-free solder alloy) over an extended period of time, ultimately resulting in electromechanical failure due to fatigue.

Regardless of package type, a customized daisy chain test vehicle is often fabricated to perform in-situ monitoring of the package-to-PCB interconnects during BLR-TC. The complexity of this daisy chain structure for WLCSP is often debated since it is not clear whether the redistribution layer (RDL) design or silicon back-end-of-line (BEOL) metal layers have any appreciable effect on the characterization of solder fatigue life. It is possible to electrically integrate the Si BEOL into the daisy chain path, albeit not without a substantial increase in foundry mask and wafer cost, and a much more involved design effort to achieve connectivity through all metal levels. Were it possible to simplify the daisy chain structure to only the packaging layers - polymer re-passivation (PM1), RDL, second polymer re-passivation (PM2), under-bump metal (UBM) and solder ball - this would reduce design complexity and the cost associated with recurring product qualifications.

This study aims to compare BLR-TC solder fatigue life between three daisy chain structures: packaging layers on full Si BEOL, packaging layers on partial Si BEOL, and packaging layers on dummy Si. The 5.022mm x 5.022mm x 0.5mm package size and 0.4mm ball grid array (BGA) pitch is consistent among all daisy chain types. Packaging layer stackup is also kept consistent at 9um PM1, 5um Cu RDL, 9um PM2, 8.5um Cu UBM and pre-formed SAC405 solder spheres. The influence of RDL layout is also captured within this comparison. In addition to physical characterization of these daisy chain structures, a well-correlated finite element model (FEM) was used to predict the solder fatigue life for each of the three cases to determine if an analytical approach is suitable for this type of structural comparison. Finally, cross-sectional failure analysis was completed to ensure that the only mode of failure for these daisy chain structures was bulk solder fatigue, contributing to higher confidence in the conclusion of this work.