Effect of Deposition Method on Grain Boundary Alignment and Off-State Leakage in Polycrystalline Silicon Channel

Polycrystalline silicon (poly-Si) is a promising channel material for three-dimensional (3D) stacked memory architecture owing to its process compatibility and excellent manufacturability. However, its practical application is hindered by intrinsic limitations, such as reduced carrier mobility and elevated off-state current (Ioff), which originate from localized electric fields and trap states at grain boundaries. In this study, the structural characteristics, including the crystallization behavior and grain morphologies, of silicon films deposited by sputtering and low-pressure chemical vapor deposition (LPCVD) were comparatively investigated. Raman spectroscopy and cross-sectional transmission electron microscopy (TEM) results confirmed that LPCVD poly-Si annealed at 800 °C exhibits over 95% crystallinity and a columnar-like grain structure. Based on this structural superiority, transistor-level electrical characterizations were exclusively conducted on LPCVD-based devices. The results show that the Ioff of annealed poly-Si depends on the channel width, with normalized Ioff values being lower when the channel is narrower than the average grain size. Further, a larger grain size with a columnar structure in poly-Si can maintain acceptable Ioff levels in 3D stacked memory devices incorporating narrow channel widths.