Dual‐Defect‐Engineered Zinc Oxynitride Thin‐Film Transistors Enabling Electrostatic Current Balancing in Geometrically Symmetric Oxide Logic

ABSTRACT

In this study, high‐mobility zinc oxynitride (ZnON) thin‐film transistors (TFTs) and geometrically symmetric active depletion‐load hybrid inverters are demonstrated. Through dual‐defect engineering of coupled oxygen‐deficient‐related defect states and nitrogen‐related disordered bonding configurations within the mixed‐anion ZnON matrix, subgap states are effectively controlled during reactive sputtering. The optimized single‐gate ZnON TFT exhibits a field‐effect mobility of 26.58 cm ²  V ⁻¹  s ⁻¹ . By dual‐gate integration, a negative threshold‐voltage shift of approximately −10 V was observed under zero top‐gate bias. Calibrated technology computer‐aided design (TCAD) simulations reproduce this behavior by introducing a localized interfacial electrostatic contribution while preserving the independently calibrated bulk response. Rather than treating this phenomenon as a process limitation, the resulting depletion‐mode operation is strategically repurposed in a hybrid n‐type metal‐oxide‐semiconductor (NMOS) inverter. Applying a negative top‐gate bias (V _TG = −10 V) to the load TFT suppresses the excess load current. This electrical pull‐down‐to‐pull‐up ratio modulation achieves current balancing without geometric asymmetry. Consequently, the inverter demonstrates a high voltage gain of 79.42 V/V together with stable rail‐to‐rail pull‐down operation. This work demonstrates a material‐device‐circuit design strategy in which process‐associated electrostatic modification is repurposed as an electrostatic circuit‐design parameter for geometrically symmetric oxide logic.