Die Backside Metallization for Low Cost High Thermal Package

Advanced semiconductor packaging

requirements for higher and faster

performance in a thinner and smaller

form factor with significantly higher

thermal dissipation continue to be the

driver for mining and artificial intelligence (AI)/high performance

computing (HPC) applications. While

the increase in device performance or

input/output (I/O) density is driven

by the famous “Moore’s Law,” the

packaging industry is experiencing

opposing trends for more complex

packaging solutions with the expected

cost targets moving downward.

Packaging technology has become more

challenging and complicated than ever before driven by advanced silicon (Si)

nodes, finer bump pitches, as well as

finer line width and spacing substrate

manufacturing capabilities to satisfy

the increasing requirements in the

semiconductor industry. As increasing I/O counts and high thermal

performance are needed in computing,

and AI/HPC devices, packaging solutions are migrating from

traditional, QFN or FLGA to flip chip

CSP (fcCSP) and high end flip chip BGA

(fcBGA) with a metallic lid to

dissipate heat. For very high pin count AI/HPC, the solution will eventually go to 2.5D with memory

integration where packaging cost is

not the primary concern. For low to

medium end computing applications,

removing the heat from the die backside without adding much packaging cost is a major challenge.

Typical thermal die power for low to

medium end thin flip chip CSP packages

is a few watts. There are various ways

to mitigate the thermal concern for

fcCSP packages such as exposing the

die backside, high conductive mold

compound, adding a metal lid to the

die backside, thicker metal layers in the substrate, die backside metallization, etc. Adding extra

packaging cost for small to medium

thermal improvement cannot be justified for a cost sensitive market.

In this study various ways of improving thermal performance of a fcCSP package are investigated and die backside metallization was finally selected as the optimum solution for

low to medium die power packages. A

thorough thermal simulation DOE was

conducted to justify the backside

metallization concept. This backside

metallization process has been integrated into high volume assembly line. Various material and processes are considered to successfully qualify

the package. The detailed assembly

process along with mechanical reliability data are published in the paper.