Development of Wafer Level Embedded SiP (System in Package) for Mobile Application

Recently the market for portable products, such as mobile phones, digital cameras, PDAs and game consoles, has been increasing rapidly and consumers like not only to carry small and light thing on the hand, but also have various functions with lower price. Accordingly, System in Package (SiP) technologies have been needed to get thin, small and light mobile products by putting various devices into only one electronic package. To satisfy the requirement, wafer level embedded system in package (WL-eSiP) has been considered and developed with the concept of wafer

level flipchip bonding one or more chips inside a bigger chip (mother chip) and wafer level molding for underfilling and encapsulation by molding compound without special substrate to realize wafer level system in package (WLSiP) with thin and small size and high performance. Firstly, to realize Wafer Level System in Package (WLSiP), its structure and dielectric and molding compound materials have been selected and verified through reliability tests of MSL2, PCT (121℃/ 100%RH/ 2atm), TC (-40/125℃) and HTS (150℃) with specified experimental molded dies with various die size, dielectric materials and mold materials and they passed MSL2, 168hrs of PCT, 2000cycles of TC and 1000hrs of HTS. After optimizing WLSiP structure and its material, WLSiP test vehicle has been designed and fabricated to evaluate the package level and board level reliabilities for verifying process and package reliability. The mother chip of 4mm x4mm has been designed in daisy chain pattern electrically interconnected each other by solder bumps that are finally interconnected with redistribution layers on mold surface and solder balls to connect with the substrate for confirmation in terms of process and package and board level reliability. Its daughter chip size is 2.95mm x 2.31mm, of which thickness is 70um. First of all, whole manufacturing process of wafer level system in package (WLSiP) has been verified and developed, with redistribution, flipchip bumping (solder and Copper), wafer level flip-chip bonding, wafer level molding, Si and mold thinning and ball mounting technologies. Then, the fabricated WLSiP has been evaluated for package level reliability tests of MSL3, PCT (121℃/ 100%RH/ 2atm), TC (-40/125℃) and HTS (150℃) and all items have been passed. For the board level reliability test, daisy chain substrate has been designed and fabricated for TC (- 40/125℃) and drop (1500G/ 0.5ms) tests and under evaluation.