Development of TSV Interposer for Control and Readout of Superconducting Quantum Annealing Circuits

Combinatorial optimization problems involve determining the optimal solution from a finite but extremely large number of combinations. Examples include logistics route optimization, drug and material development, and manufacturing process optimization. When solving combinatorial optimization problems using conventional computers with classical bits, calculations are performed for each combination, which requires an extremely long time when the number of combinations is large. Thus, quantum annealing machines are attracting attention as a method for solving this problem because they use quantum bits, which are superpositions of 0 and 1, thereby allowing calculations to be performed in an extremely short time. High-quality quantum bits and quantum-annealing circuits are essential for realizing this quantum-annealing machine. To this end, the NEC Corporation previously developed superconducting quantum annealing circuits using superconducting parametrons to solve combinatorial optimization problems with high speed and accuracy. The use of superconducting parametrons [1,2] renders this quantum-annealing machine resistant to noise and enables a long coherence time, that is, duration for maintaining the quantum state. Furthermore, the NEC Corporation successfully fabricated a superconducting quantum annealing circuit with eight qubit cells using superconducting parametrons and confirmed its operation using aluminum wire bonding technology. However, numerous power supplies and high-frequency signal readouts are required to operate many qubits.

In this study, we developed a through-silicon via (TSV) interposer for control and readout of superconducting quantum annealing circuits. This process involves 16 steps: (a) deposition of hard mask; (b) hard mask etching; (c) deep Si etching; (d) hole cleaning to remove the photoresist and hard mask; (e) barrier-seed layer deposition; (e) electroplating for Cu filling; (f) chemical mechanical polishing (CMP), (g) formation of surface protection layer to protect the TSVs; (h) SiO2 bump formation; (i) formation of superconducting frontside interconnect; (j) Ti-In electrode formation; (k) bonding of support glass direct Si/Cu grinding and CMP for backside TSV reveal; (l) formation of backside insulator; (m) formation of backside interconnect with superconductivity (Ti-Al layer); (n) backside passivation layer formation; (o) opening of passivation layer; and (p) Ti-Au electrode formation. 

Furthermore, we stacked the qubit chips on TSV interposers and evaluated the qubits inside a dilution refrigerator. As a result, we confirmed that controlling the qubits and readout qubit signals via the TSV interposer is possible, and that the qubits operate correctly.