Design-Space Exploration for Runtime-Reconfigurable FPGA-Based DNN Accelerators

Deep Neural Networks (DNNs) have recently achieved major gains across many domains, increasing the need for hardware accelerators that can adapt to changing workloads. Because DNN layers have diverse characteristics, each may benefit from a different hardware architecture. FPGAs support this through runtime reconfiguration, but applying it to neural network accelerators remains limited. Reconfiguring the FPGA between every pair of layers would tailor hardware to each layer but incur prohibitive reconfiguration overhead. We address this by proposing a cluster-based approach that groups layers with similar computational requirements and assigns each group a shared hardware configuration. This reduces the number of reconfigurations while preserving efficient execution. However, selecting good clusters and configurations creates a large design space, especially for large networks: too few clusters merges dissimilar layers and hurts efficiency, while too many clusters increases reconfiguration overhead. To tackle this, we present a Design-Space Exploration (DSE) framework that co-optimizes clustering schemes and hardware configurations using genetic algorithms. Our method explores clustering schemes without accuracy loss, as the network and numeric precision remain fixed. Unlike prior work that optimizes only hardware or only mapping, our approach jointly optimizes both. We show that reconfiguring at carefully chosen points reduces overall inference latency despite reconfiguration costs. On GPT-2, ResNet-18, VGG01, VGG02, and AlexNet, our cluster-based designs reduce latency by 20–43% versus a fixed architecture and outperform the Simba and Eyeriss accelerators on four of five models while matching performance on VGG02.