DOI: 10.3390/photonics13070621 ISSN: 2304-6732

Design of Silicon Photonics Metasurface Enabling Optical Interfacing for Co-Packaged Optics

Constantinos Haliotis, Georgios Syriopoulos, Giannis Poulopoulos, Dimitrios Apostolopoulos, Hercules Avramopoulos

The exponential growth of AI-driven data traffic necessitates the evolution of Data Center Networks toward high bandwidths and sub-microsecond latency. While co-packaged optics (CPO) offer a pathway to reduced energy consumption and increased capacity, they introduce significant challenges in optical chip coupling and packaging complexity. This study explores monolithically integrated metasurfaces as an alternative for optical interfaces, potentially reducing the need for bulky external microlens arrays or extremely precise mechanical alignment. We design an amorphous silicon (a-Si) metasurface on a Silicon-On-Insulator (SOI) platform operating at 1310 nm. By spatially mapping nanopillar radii to satisfy a spherical phase profile, we achieved near-vertical beam emission with an emission angle of 0.88° focused at a focal length of 98.99 μm. Broadband characterization across a 20 nm band confirms stable focusing and a confined spot size with moderate roll-off toward the band edges. The sensitivity of the emission profile of the device to fabrication imperfections in pillar radius, height, and sidewall taper is quantified. The coupling to a polymer-based optical redistribution layer (ORDL) is also studied, and the corresponding modal analysis demonstrates a maximum coupling efficiency of 68.2% into an SU-8 polymer waveguide. Tolerance analysis results reveal deterioration of 0.9 dB and 0.4 dB for ±0.6 μm horizontal and ±1.5 μm vertical misalignment respectively, making the interface compatible with relaxed alignment assembly assumptions, although experimental packaging validation remains required. The methodology is further validated at 1550 nm, demonstrating its applicability across telecom bands. These results suggest that integrated metasurfaces may simplify the packaging stack and enhance density for next-generation CPO links by providing precise, on-chip wavefront manipulation.

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