Design of Low-Complexity and High-Speed Reconfigurable FIR Filter Using a Modified Distributed Arithmetic Structure

The implementation of Software-Defined Radio (SDR) requires various reconfigurable modules. One of the important modules is the reconfigurable finite impulse response (FIR) filter, which SDR has to support different wireless standards by reconfiguring the single filter structure. The complexity of implementing these filters depends on the method of changing coefficients, which can be resolved using the coefficient decimation method. This paper presents a Distributed Arithmetic (DA)-based reconfigurable FIR filter employing the Coefficient Decimation method (CDM) to achieve a low-complexity and scalable hardware architecture for Software Defined Radio (SDR) applications. FPGA synthesis results demonstrate approximately proportional resource growth with increasing filter order, requiring 400, 950, 2200, 4680, and 9800 LUTs for the 32-, 64-, 128-, 256-, and 512-tap implementations, respectively. The design operates at maximum frequencies of 165 MHz and 150 MHz, while consuming only 145 mW and 295 mW of power for the 128-tap and 256-tap configurations, respectively, without the use of dedicated DSP blocks. In addition, the proposed architecture achieves the lowest LUT-per-tap ratio among the compared designs, highlighting its efficient utilization of FPGA resources. Overall, the results demonstrate that the proposed CDM–DA architecture provides an effective trade-off among hardware resource utilization, operating frequency, power consumption, and scalability, making it a promising solution for high-order reconfigurable FIR filters in SDR channelization, multirate signal processing, and adaptive filtering applications.