Design and Reliability of μPILR™ Package-on-Package (PoP)

Manufacturers are increasingly challenged to meet reliability, performance, form factor and cost objectives for today’s enhanced mobile electronics. 3D packaging is fast becoming the package design of choice to overcome the technical limitations of conventional interconnect technology. 3D packaging solutions are available in several forms, some of which are chipstack, package-in-package (PiP) and package-onpackage (PoP). Each version has its own advantages and disadvantages, with chip-stack and PiP offering smaller size and higher internal IO, and PoP offering greater yield and system flexibility.

In this paper, the current design possibilities of PoP for leading-edge, feature-rich mobile electronic applications are presented. The impact of package miniaturization on memory and logic package IO is presented. The design trade-offs of different designs and their features and limitations are listed. A new form of interconnect called the μPILR platform is presented in the PoP format. This technology is characterized by 3D interconnects made of solid copper that enable high aspect ratio interconnects, which enable higher IO and finer pitch for the top layer and larger gap between bottom IO for more trace escapes on the main board.

To characterize this technology, the μPILR PoP solution was fabricated and tested for reliability. Assembly results have shown that the SMT yield at fine pitch is significantly higher as compared to that of conventional solder ball PoP. Thermal cycling and drop tests results show the μPILR PoP solution to have high reliability, especially for drop tests. Failure analysis has shown that the μPILR technology interconnect acts as a crack growth inhibitor and therefore increases the lifetime under dynamic loading.

In conclusion, the design, analysis and reliability results show that μPILR PoP technology meets industry requirements for miniaturization without compromising yield or reliability.