Demonstration of <5nm Overlay Distortion for Backside Power Delivery Through Control of Wafer Conditions and Processing

A backside alignment test vehicle was created to evaluate overlay distortion due to bonding for backside power delivery. Void-free fusion bonding was demonstrated with a simulated overlay distortion of <4.5nm M+3σ after six term correction per exposure field (CPE6). After rework and application of this correction to the wafer the actual distortion was <7nm M+3σ with 90% of the wafer below 4nm. Removal of scanner noise shows the estimated contribution to distortion due to the bonding process of <3nm M+3σ.

A major impediment to continued scaling of logic and memory is the space needed for signal and power lines above the device. The most promising solution to this issue is integration of a bonding step into the device flow and moving the power lines from the frontside to the backside of the device. This can be either a fusion bond, where the device and signal lines are coated with dielectric and bonded to a carrier wafer or hybrid bonding enabling electrical connection of the device wafer to other patterned structures. After the bond the wafers are annealed at low temperature (200-400 °C) to condense the dielectric bonds and for direct Cu-Cu bond formation in the hybrid bonding case. This independent optimization of power and signal networks improves overall device performance and enables further reduction of standard cell tracks. Unfortunately, during the bonding process the device wafer pattern is distorted, which impacts lithographic overlay degrading the yield of the backside power contacts. Initial schemes were less stringent with specs of <20nm overlay misalignment, but as more advanced schemes are implemented this target will be reduced to <4nm across the wafer. To meet this overlay target a fundamental understanding of bonding induced distortion is required.

 To demonstrate <4nm overlay distortion a backside power delivery network test vehicle was developed. This test vehicle contains a dense array of overlay alignment marks across the die to understand the local changes in wafer position during the wafer build, bonding process and patterning steps. After integration, wafers were bonded with a TEL bonder and a low distortion bonding recipe was developed to eliminate distortions that are not correctable by the bonder. This results an wafers with initial measured overlay of ~80nm M+3σ but this value reduces to <4nm M+3σ after CPE6. The main sources of uncorrectable misalignment are the bond initiation point, the wafer edge and a ring along the mid radius of the wafer due to stress induced by the bonding process. Through bonder tuning the center distortion can be reduced by 90% and the stress ring can be fully eliminated. For the edge distortions, these can be corrected by the bonder as well as improvements to the incoming wafer conditions, mainly the rolloff of the dielectric at the edge of the wafer. Co-optimization the bonding process and incoming edge rolloff can reduce the distortion at the wafer edge by >50%.

While these results post-correction are adequate for future needs. It can be time consuming to apply corrections to every wafer. To reduce the need for by-wafer correction, further work has been carried out to understand how the integration flow, surface preparation and bonding process impact the linear components of the distortion as well as the wafer-to-wafer variations. The largest contributing factor to the linear distortion is the surface composition, while the main contributor to the wafer-to-wafer variation is the integration flow. Within each material set altering the thickness, polishing and activation conditions leads to a corresponding change in the stress induced distortion during the bonding process. The wafer-to-wafer variations arise as tools with multi wafer processing capabilities but systematic fingerprints on the wafer based on position in the batch.  By incorporating this learning into future bonding integration schemes the need for by wafer higher order corrections can be eliminated through multi-module solutions to meet the needs of each bonding material set.