Current-Feedback RST Thrust Regulation Within a Nested Saturation Attitude Loop: Design, Embedded Realisation and Characterisation on 8-Bit Hardware

Advanced quadrotor control is validated predominantly in simulation or on 32-bit floating-point flight computers, leaving open whether comparable architectures are deployable on the low-cost 8-bit hardware common to small-scale platforms. This paper reports the design, embedded realisation and experimental characterisation of a two-level discrete-time architecture for a 1.56 kg quadrotor implemented entirely in bare-metal C on an ATmega 2560. The actuator level departs from open-loop commanding of the electronic speed controllers: a discrete-time RST regulator closes a thrust loop around the bus current through a fourth-order calibration whose coefficients are reported, fitted to 615 bench points with a coefficient of determination of 0.998. The supervisory level combines proportional–derivative regulation of altitude and yaw with a nested saturation law for roll and pitch. The synthesised inner loop attains a modulus margin of 0.43 and a delay margin of 0.67 samples, tolerating approximately 43 percent multiplicative plant uncertainty. Bench records give a measured inner-loop rise time of 60 ms, which against the measured outer-loop rise time of 310 ms corresponds to a bandwidth separation of 5.2 to 1. Attitude experiments give rise times of 0.31 and 0.32 s and a residual roll offset of 2.04 degrees. The inner loop is found to exhibit approximately 49 percent overshoot despite a damping specification of 0.7, and this rather than time-scale separation is identified as the likely origin of the measured attitude transients. No comparative performance claim against conventional architectures is made.