Cost Analysis of Panel-level Packaging for HPC and AI Applications

The idea of using square or rectangular panels instead of round wafers has been a topic of interest in the microelectronics packaging industry for years now. A more recent addition to the discussion is the potential to use panels for advanced packaging applications. This contrasts with some earlier panel-level analyses that primarily focused on smaller, basic fan-out packages. Whether evaluating panels for simpler or more complex packages, one primary focus of any panel-level discussion is the potential for cost savings.

The author proposing this paper has already carried out some cost analysis of panel-based packaging. However, the previous analysis centered on traditional fan-out packaging and large panels (600x600mm). The cost analysis for this paper will have a new and different focus. First, the panel size evaluated will be a square 310x310mm panel. Second, large and complicated packages will be used as example designs. And finally, advanced fan-out packaging will be evaluated instead of the more basic fan-out that was previously analyzed. 

The goal of this paper is to present potential cost savings for large packages built with advanced fan-out technology using a 310x310mm panel formfactor in place of a 300mm wafer.