Charge-Margin-Oriented Write-Energy Optimization for Low-Power OSFET 2T0C DRAM Array

Back-end-of-line-compatible oxide-semiconductor field-effect transistors (OSFETs) enable vertically stackable two-transistor zero-capacitor (2T0C) dynamic random-access memory (DRAM) cells, offering high densities while maintaining low write energy. The capacitorless 2T0C cell intrinsically benefits from decoupled read/write paths and a sub-fF storage-node (SN) capacitance CSN, reducing the stored charge to the sub-fC level. However, the control-line energy overhead introduced by the independent write word-line (WWL) activation can erode this advantage. The minimum write energy is ultimately bounded not by CSN alone but also by the drive capability and leakage of the write transistor TW and the WWL and write bit-line (WBL) voltage configuration. A systematic co-optimization methodology addressing these coupled constraints has yet to be established. This work is built on the insight that the write-optimization target should be the stored-charge margin ΔQSN rather than the storage-node voltage VSN because ΔQSN remains nearly constant across all phases and directly governs readout distinguishability. The methodology combines a coupled analysis of threshold voltage (Vth), SS, and μFE of TW with the adoption of ΔQSN as the read-margin metric. On this basis, the write-overdrive margin, the WBL voltage, and Vth of TW are sequentially optimized. The three-step procedure reduces ΔVWWL from 3.0 V to 2.10 V while satisfying the 2 ns design-level write-time constraint, the 0.54 fC read-margin criterion, and the 1 ks retention benchmark. Under the assumptions of the present case study, the optimized 2T0C array yields a 2.5× reduction in array-level write-related energy relative to the unoptimized baseline and a 3.0× reduction relative to the LPDDR6 1T1C array reference.