Automated Synthesis of System Simulation Models from Function-Oriented System Architecture Models for HiL Testing

Today, the development of electrified commercial vehicles requires efficient validation methods that enable early system testing while maintaining consistency between development and testing models. Hardware-in-the-Loop (HiL) testing provides a suitable approach by combining real hardware with executable real-time simulation models. However, HiL models are typically created manually for specific test cases, resulting in high modeling effort and limited reuse of development knowledge. This paper presents a methodology for the automated synthesis of executable, test-specific system-level HiL simulation models from predefined and reusable simulation components based on function-oriented SysML system architecture models. The approach combines filtering of architectural data, automated analysis of model availability and parameter completeness and configurable selection of the desired model fidelity. Reusable simulation components aligned with the system architecture are automatically selected, parametrized, connected, and aggregated into executable Simulink HiL models including test-bench interfaces. The methodology was validated for three electrified vehicle architectures and deployed on a dSPACE-based HiL test bench for drivetrain functionality and range analyses. The generated system-level HiL models were created in a few seconds while maintaining consistency with the central MBSE system architecture.