Application of Picosecond Acoustic Metrology for monitoring Metal Films in Advanced Packaging
M. Mehendale, K. Park, Y. T. Han, J. Dai, C. Kim, G. A. Antonelli, P. MukundhanHigh-performance computing applications such as artificial intelligence, and machine learning require massive amount of parallel processing requiring significant memory bandwidth. High bandwidth memory (HBM) solutions have been optimized to enable such applications. HBM consists of core DRAM die and a logic buffer die in a vertically stacked 3D structure. Customers are adopting front-end solutions to meet the shrinking process tolerances and to meet the stringent reliability requirements. [1]
Picosecond acoustic metrology is a well-established technique for in-line measurements [2-3] and can be applied to meet the challenges of advanced packaging applications. In this paper, we shall present system-level improvements and specific use cases that have accelerated adoption of the technology in fan-out wafer level packaging (FOWLP) and in the HBM process loop. In the FOWLP process, re-distribution lines (RDL) play a critical role in how I/Os are connected and measuring RDL thickness before and after copper seed etch is necessary as it impacts line resistance and leakage current. In the TSV process loop, multi-layer metal stack such as gold/nickel/copper is used to form pads for bonding to the micropillar. The thickness of each of the layers plays a critical role in reliability performance and hence in-line process control requires layer to layer thickness monitoring is. Similarly, in the microbump process flow, controlling copper seed/barrier thickness is critical as the relative bump heights will vary as a function of the copper seed thickness variation impacting bump co-planarity [4-5].
References
1. S. Ha, S. Lee, GH. Bae, DS. Lee, S.H. Kim, BW. Woo, N-H Lee, YS. Lee and S. Pae, “Reliability Characterization of HBM featuring HK+MG Logic Chip with Multi-stacked DRAMs,” 2023 IEEE International Reliability Physics Symposium (IRPS), May 2023 2. J. Dai., J. Chen, M. Mehendale, M. Alves, J. Ding, F. Shen, R. Mair, A. Hegde, P. Mukundhan, J. Shen, C. Kim, “Comprehensive In-line Metrology for Advanced RDL Process Monitoring”, IMAPS 2017 3. Parker Huang, Bruce Chiu, Jay Chao, Chun Hung Lu, Stephen Chen, Jay Chen Fei Shen, Jian Ding, Johnny Dai, Priya Mukundhan, and Timothy Kryman., Optical and Acoustic Metrology Techniques for 2.5D and 3D Advanced Packaging, In Proceeding of the IMAPS Device Packaging, San Diego, 2014. 4. J. Derakhshandeh, Inge De Preter, Carine Gerets, Lin Tong Hou, N. Heylen, Eric Beyne, Gerald Beyer, John Slabbekoorn, Vikas Dubey, Anne Jourdain, Goedele Potoms, Fumihiro Inoue, Geraldine Jamieson, Kevin Vandersmissen, Samuel Suhard, Tomas Webers, Giovanni Capuz, Teng Yue Wang, Kenneth June Rebibis, Andy Miller, “3D Stacking Using Bump-Less Process for Sub 10µm Pitch Interconnects,” ECTC 2016 5. C. Chen, D. Yu, and K. Chen, “Vertical Interconnects of Microbumps In 3D Integration,” MRS Bulletin, Vol. 40, March 2015, 257-262