APEC-Route: Guiding Analog Routing with On-the-Fly Parasitic Extraction Based on a Neural Capacitance Model

Analog routing must balance design rules and layout constraints while managing interconnect resistance and capacitance. Many analog-routing frameworks combine wirelength objectives with constraint handling and evaluate detailed parasitic effects after routing. This separation motivates investigating whether low-latency parasitic estimates can guide candidate expansions during routing. We present APEC-Route, an analog-routing framework that combines interval-tree-based wire segmentation, a multilayer perceptron (MLP)-based neighbor-aware total-capacitance model, and analytical wire-resistance evaluation. The resulting estimates guide the search in parasitic-minimization and parasitic-matching modes. On four finalized 65 nm layouts, the extractor attains a geometric-mean relative error of 5.54–6.77% and a mean absolute percentage error of 7.41–9.93% against the field-solver reference; each in-search query takes 251–345  μ s. For each of three 65 nm block-level routed-circuit cases—an operational transconductance amplifier (OTA), a comparator, and a capacitive digital-to-analog converter (CDAC)—SAGERoute and the w/o-R/C, R-only, CC-only, and full APEC-Route variants use the same fixed placement. Across both controlled capacitance-term comparisons, enabling the capacitance term improves eight of nine independent circuit metrics, with OTA phase margin as the sole exception. The derived ENOB increases consistently with SINAD. Relative to w/o R/C, the full objective increases OTA gain and CMRR by 2.7 and 1.0 dB and UGB by 0.01 MHz, reduces comparator delay, hysteresis voltage, and offset voltage by 20.5%, 16.0%, and 26.6%, and reduces CDAC delay by 10.4% while increasing SINAD by 16.4 dB; OTA phase margin decreases by 1.1°.