Analysis and Design of a Cross‐Scale Current‐Sensing Readout Chain With Hybrid‐Domain Collaborative Optimization

ABSTRACT

This paper presents the analysis and design of a cross‐scale current sensing readout chain based on a hybrid‐domain collaborative optimization approach. The front‐end employs a discrete‐time correlated double sampling capacitor‐coupled transimpedance amplifier (CDS‐CTIA) to introduce deep near‐DC high‐pass noise shaping to effectively suppress low‐frequency flicker noise and DC offset. Concurrently, the secondary stage incorporates a continuous‐time chopping‐stabilized fully differential difference amplifier (Chopper‐FDDA), which upconverts residual offset spectra and mitigates the thermal noise folding penalty inherent in discrete‐time sampling. Furthermore, leveraging the dynamic class‐AB linear steady‐state behavior of the FDDA, governed by a transconductance‐loop control scheme, the readout chain effectively absorbs transient switching artifacts and supply‐rail disturbances across the entire full‐scale input range. The readout chain is implemented using a standard 180‐nm CMOS process and verified at a 1.8 V supply, supporting a wide range of bidirectional input currents from 54 to +54 nA, without suffering from virtual‐ground saturation. Post‐layout simulation results demonstrate that the proposed system achieves an ultra‐low integrated input‐referred noise of 1.40 pArms over a 0.1–100 Hz band, corresponding to a dynamic range of 91 dB and an excellent overall global linear fitting degree of 99.9%. The overall design power consumption is 70.1 , with a core layout area of only 0.0094 , providing an efficient solution for weak current‐mode analog‐to‐digital interface conversion.