Analysis and Control of Capacitor-Based Serial Chain-Link MMC with Reduced DC-Blocking Capacitor

The series-connected chain MMC with DC-blocking capacitor (C-SCMMC) is an emerging topology for HVDC tapping applications with high voltage and relatively low power capacity. However, the DC-blocking capacitor can be bulky and costly, which deteriorates its economy and flexibility. This paper investigates the feasibility of DC-blocking capacitor reduction, with special emphasis on the characteristics, control, and parameter design. The principle of C-SCMMC considering the DC-blocking capacitor dynamics is firstly modeled and analyzed, and the ripples and harmonics, as well as their influences on the external performance of the converter, are analyzed; then, improved control strategies, namely, the grid-tied harmonics suppression and current control, are proposed considering the enlarged DC-blocking capacitor voltage ripple; after that, the influence of reduced DC-blocking capacitor on the operation range and parameter design are analyzed, and the economic advantage is demonstrated via parameter design and comparison based on a typical bench mark. Analysis shows that the DC-blocking capacitor voltage ripple is coupled with other parameters, such as the arm output voltage and SM capacitance, and the advised range is from 0.1 to 0.3 p.u. at unity power factor to reduce the overall cost. In a typical design, the C-SCMMC can reduce the number of SMs by 2/3 and the capacitor energy storage capacity by 15% compared to the conventional MMC. Finally, simulation results obtained in MATLAB/Simulink 2024b are provided to verify the feasibility of the proposed converter and the correctness of the parameter design.