An On-Chip-Calibrated Coarse-Fine FPGA Time-to-Digital Converter for Single-Photon LiDAR: Design and Experimental Validation

Long-range single-photon LiDAR requires both a wide time-of-flight (ToF) dynamic range and fine temporal resolution, while the nonuniform fine-time bins of FPGA carry-chain tapped delay lines (TDLs) can introduce systematic errors into time reconstruction. This work presents a coarse-fine FPGA time-to-digital converter (TDC) with on-chip code-density calibration implemented on a Xilinx Kintex-7 XC7K325T device. A 250 MHz coarse counter is combined with a CARRY4-based TDL for sub-cycle fine-time quantization, and code-density accumulation, lookup-table (LUT) construction, and calibrated time reconstruction are implemented on the FPGA. Using 201,086 valid calibration events, the measured mean valid-bin width is 12.08 ps. The calibration LUT exhibits R2 = 0.9998, with an RMS fit residual of 14.80 ps and a maximum absolute residual of 59.78 ps. Independent measurements at representative reference intervals from 0.2 to 2.0 μs show a maximum absolute mean error of 3.064 ps. The routed implementation uses 1564 Slice LUTs, 3537 Slice registers, 16 RAMB36 blocks, and no DSP resources. The TDC is further integrated into a single-photon LiDAR system and validated on targets at approximately 0.86 and 3.05 km, where repeated-ranging standard deviations of 0.029 and 0.035 m, respectively, and depth imaging are obtained. The approximately 1 ns end-to-end temporal response is dominated by the optoelectronic chain rather than the TDC quantization, indicating that the fine TDC resolution prevents the digital timing stage from becoming the system bottleneck and leaves margin for lower-jitter future systems.