An Observer–Data-Path Decoupled Time-Domain ADC with Three-Stage Digital Background Calibration in 28 nm CMOS

This paper presents an observer–data-path decoupled time-domain ADC with three-stage digital background calibration, designed and comprehensively verified through post-layout simulations in 28 nm CMOS for highly integrated micro-systems. In scaled nodes, the voltage-to-time converter front-end exhibits large-signal nonlinearity, while the time-to-digital converter (TDC) resolution drifts with PVT; conventionally these two errors are strongly coupled in the time domain, making concurrent calibration difficult. To break this coupling, the proposed observer–data-path decoupled architecture confines a single-bit pseudo-random dither to an observer path for error extraction and reconstructs the signal in a dither-free data path, thereby separating the calibration loops without degrading the SNDR. Building on this decoupling, a constant time-offset injection logic eliminates the gated ring oscillator-TDC dead-zone, and the three-stage calibration compensates the ADC gain error induced by TDC-resolution drift through VTC-gain tuning, regulates the non-integer dither ratio through Bang-Bang control, and suppresses the residual even- and odd-order nonlinearity through a dither-modulated threshold-crossing algorithm with EWMA-filtered LMS polynomial adaptation. In post-layout simulation at 1 GS/s, the calibration lifts the near-Nyquist SFDR from 50.3 to 67.0 dBc and the SNDR to 46.0 dB, and improves the INL to −0.15/+0.70 LSB. The design consumes 2.98 mW under nominal conditions and 3.89 mW at the worst-power PVT corner, corresponding to nominal and worst-case Walden FoMs of 18.3 and 23.9 fJ/conversion-step, respectively, within a 0.0024-mm2 core.