An Approach for Testing of Embedded Interconnects that Bypasses the Interconnect Isolation Logic

In a chiplet-based design, logic blocks (chiplets) are connected by a large number of interconnects to form larger functions. The interconnects require comprehensive testing to ensure that the design operates correctly. The interconnects are tested using isolation logic to support comprehensive structural testing. It was also suggested to test the interconnects together with the logic block that drives them in a closer to functional mode of operation. In this approach, fault effects are captured at the destination of the interconnects. Whereas the isolation logic on the source of the interconnects is bypassed, the isolation logic on their destination is not. This article suggests for the first time an approach where the isolation logic on both the source and destination of the interconnects is bypassed, operating the same as during functional operation. This requires an interconnect fault model that specifies fault effects. In addition, sequential test generation is used for more complete testing under functional operation conditions. Sequential test generation is applied only to interconnect faults to limit the computational effort. To further limit the computational effort, the article introduces a notion of potentially undetectable interconnect faults that is specific to this model. Experimental results for benchmark circuits in an academic simulation environment demonstrate the effectiveness of sequential test generation in this context.