Ambipolar Transistors Based on Vertical Heterojunctions for Multivalued Logic Gates

Multivalued logic (MVL), which encodes information beyond binary states, offers a transformative approach to enhancing computational efficiency in the post‐Moore era. Conventional MVL implementations typically rely on lateral heterostructures that exhibit negative differential transconductance (NDT) or negative differential resistance (NDR) behavior. However, such designs are often hindered by fabrication complexity and sensitivity to voltage thresholds. Here, we present a simple and effective strategy for MVL devices: a vertical heterojunction architecture with a self‐assembled monolayer (SAM)‐modified interface. The SAM not only passivates surface defects but also spatially confines hole carriers. This yields a distinctive V‐shaped transfer characteristic with suppressed hole conduction, a feature critical for achieving stable intermediate logic states without the need for intricate multithreshold engineering. We further demonstrate a ternary inverter with three distinct logic states, whose intermediate state range is dynamically tunable via supply voltage in the subthreshold regime. Our work provides a promising pathway toward energy‐efficient MVL systems for applications in artificial intelligence and edge computing.