AI PDN Performance and Efficiency Improvement Enabled by Saras STILE(TM)

Generative AI applications are transforming the semiconductor landscape, driving the need for advanced power delivery solutions to meet increasing demands for efficiency and performance. AI workloads are anticipated to continue straining energy and electricity infrastructure, with estimates suggesting that by 2030, over 15% of electricity consumption in the U.S. will be dedicated to AI. AI-specific accelerators require robust power delivery networks capable of providing thousands of amps at extremely low voltages to deliver over 2000W of power. 

Current power delivery networks (PDNs) remain predominantly lateral in design, leading to inefficiencies that necessitate hundreds of passive components and an ever-increasing number of power modules. This paper presents innovative solutions in highly-integrated passive components, specifically capacitors and inductors, while analyzing the system-level impact of their integration points. Additionally, we introduce Saras’ advanced eVR STileTM (embedded voltage regulator) technology, designed for vertical power delivery architectures that enable more efficient PDNs.

Traditional PDNs are nearing their physical and technological limits to deliver the required energy within constrained space. Recent trends in AI products show increasing package body sizes, growing silicon area, and rising power densities—all creating a feedback loop where more power is needed, yet space for components and modules is shrinking. This paper proposes an innovative approach that embeds high-performance, highly customizable passive components to enhance overall power efficiency and facilitate true vertical power delivery architectures. These architectures can be implemented through Saras’ technology at both the substrate and power module levels.

For the first time, this paper presents a comprehensive system-level analysis of embedded capacitors and inductors, evaluating their impact on overall PDN performance. Emphasis is placed on the best-in-class performance and reliability of these embedded capacitors within substrate environments. The results demonstrate minimized power path lengths, achieving a total PDN efficiency of over 80%, thereby enabling more power-efficient and higher-performance pathways for AI applications.

Saras’ highly integrated eVR (embedded Voltage Regulator) substrates empower package designers to incorporate increased silicon functionality, surpassing current power delivery capabilities. Ultimately, this work demonstrates, for the first time, that power densities exceeding 5A/mm² can be managed through the adoption of vertical power delivery architectures enabled by Saras’ eVR STileTM technology. Saras will introduce for the first time our generation 2 capacitor technology and the impact that it brings when applied to vertical power delivery technologies.