Advancing Low-Temperature Hybrid Bonding via Tailored Copper Microstructure Engineering

The growing demand for high-density interconnects in advanced packaging technologies has intensified the need for robust and scalable hybrid bonding solutions. Conventional copper-to-copper (Cu-Cu) bonding methods, which typically rely on coarse-grained copper (cg-Cu), require processing temperatures above 300 °C. Such elevated temperatures pose significant challenges for device integration, including potential damage to sensitive integrated circuits. To address these limitations, alternative copper microstructures—such as nanotwinned copper (nt-Cu) and metastable fine-grained copper (fg-Cu)—are being actively explored. While nt-Cu offers enhanced atomic diffusivity and supports lower bonding temperatures, it often falls short in via filling performance. In contrast, fg-Cu exhibits promising recrystallization behavior during annealing, which facilitates high diffusivity and improved Cu-Cu interface quality. However, maintaining the metastable fine-grain structure during wafer queue times remains a key challenge.

This study presents a next-generation electrochemical deposition (ECD) copper electrolyte capable of producing structurally stable fg-Cu deposits. These deposits retain their fine-grained microstructure for extended periods under ambient conditions and exhibit favorable recrystallization behavior upon thermal treatment. Additionally, the electrolyte demonstrates excellent via filling capabilities, making it suitable for both wafer-to-wafer (W2W) and die-to-wafer (D2W) bonding processes. Comprehensive microstructural characterization techniques were employed to assess grain stability and identify critical influencing parameters. The results show that, with optimized additive formulations, the fg-Cu structure remains stable for over four weeks, significantly extending process flexibility. These findings highlight the potential of engineered fine-grain copper as a key enabler for next-generation, low-temperature hybrid bonding, aligning with the stringent integration requirements of advanced 3D-stacked semiconductor devices.