Advanced Wafer-Level Integration Technology with Ultra Fine Pitch Redistributed Layers Between Heterogeneous Devices

The authors have proposed Pseudo-SOC Technology realizing integration of heterogeneous devices with resin and have established basic key technologies. In this paper, the authors show summary of the technology as well as the results of the ultimate refinement of redistributed layer on the pseudo-SOC as the state of the art. It is indispensable to integrate heterogeneous devices with narrow gap and to interconnect them with fine pitch redistributed layer (global layer) to realize high-density integration in the pseudo-SOC. Vacuum printing condition was optimized for forming resin in the narrow gap without voids. The step was also reduced to less than 1μm by optimizing the condition of mounting devices and forming planar layer. Adhesion of the redistributed layer was also optimized by tuning the formation condition of planar layer. The etching condition was also optimized for reducing the line width of the redistributed layer. As a result, a fine pitch redistributed layer with as narrow as 1μm/1μm in line/space was realized on the pseudo-SOC by using wet etching technique. Finally, a pseudo-SOC where LSI and MEMS were integrated and connected with fine pitch redistributed layers was fabricated successfully as a demonstration of this technology. From these results, it was confirmed that high density integration of heterogeneous devices is realized by the advanced pseudo-SOC technology.