Active Demonstration of a Passively Self-Aligned, Multi-Chip Package using Proximity Communication in a Switching Fabric

Recently, we introduced a novel chip packaging platform based on the passive self- alignment of chips into 2D arrays, which extends the physical area of fully integrated CMOS VLSI silicon chip beyond the area of the single chip reticle [1]. We report the first active demonstration of this packaging concept, in which functional chips are configured in a face-to-face geometry with sufficient alignment accuracy to enable Proximity Communication (PxC): chip-to-chip capacitively coupled communication between overlapping metal pads [2]. The key advance reported here is a low-cost packaging application of selfaligning precision microballs and etched pits in CMOS for successful high fidelity PxC signaling. Creating these pyramidal wafer pits required co-integrating silicon micromachining into a 180 nm CMOS technology. Our demonstration vehicle is an active switching fabric composing a four chip linear vector array [3]. Atop these four face-up “island” chips sit face-down “bridge” chips, such that data can be coupled between four islands via overlapping bridges. Inverse pyramidal pits on both bridge and island chips are photolithographically defined relative to the capacitive micropads. In our demonstration 300 micron diameter microballs precisely lock the chips in global alignment to within a micron and PxC signaling is achieved across array without error. This assembly has relaxed manufacturing tolerances: up to half the microball diameter in placement inaccuracy still leads to precise self-alignment to within a couple of microns.