A Temperature‐Robust Subsampling PLL With 74.4‐fs Jitter and −251.2 dB FoM in 65‐nm CMOS

ABSTRACT

This paper presents a highly robust integer‐N subsampling phase‐locked loop (SS‐PLL) achieving low jitter and high immunity to process‐voltage‐temperature (PVT) variations across an automotive temperature range (−40°C to 125°C). The design incorporates a current‐based high‐slew‐rate sampling buffer in the subsampling phase detector (SSPD) to stabilize phase detection gain while suppressing spurs. Furthermore, it employs a temperature compensation technique to maintain charge pump transconductance ( G _m ) stability and effectively cancel the thermal frequency drift of the inductor‐capacitor voltage‐controlled oscillator (LC‐VCO), thereby significantly enhancing the robustness of the loop against temperature variations. Fabricated in 65‐nm CMOS, the prototype measures 74.4‐fs root‐mean‐square (RMS) jitter (integrated 1 kHz–100 MHz), a reference spur of −70.68 dBc at 2 f _REF , and a competitive jitter‐power figure of merit (FoM) of −251.2 dB while consuming 13.8 mW. Crucially, it maintains lock and stable performance with the RMS jitter remaining within 69.2–82.1 fs from −40°C to 125°C without VCO band switching, validated by measurements across temperature, supply voltage, and multiple chips.