A Study on RTL Implementation of Thinning and Gabor Filter Algorithm Using GDI and CMOS Hybrid Library

Abstract

In this paper, we propose a GCMOS library that optimizes the advantages of CMOS and gate diffusion input (GDI) circuits and propose a new RTL design flow for applying the GCMOS library. We design a Gabor filter and a thinning accelerator, which account for the largest computational load in a fingerprint recognition algorithm, by applying the proposed design flow. The accelerator is designed using 1.8 V, 180 nm CMOS and the GCMOS library, respectively. In the PPA analysis, the GCMOS accelerator showed about a 31% reduction in chip area compared to conventional CMOS and similar results in power consumption and operating speed. The results of this study show that GDI circuits can be applied to the RTL design method of system-on-chip and can significantly reduce the area under the same conditions.