A Stochastic Coolability Analysis For A Microprocessor Considering Chip Power Fluctuation

As process technology continues to evolve, the shrinking gate sizes in today’s microprocessors are accompanied by a notable increase in the die power. While increased power is a challenge to the cooling design in its own right, another significant aspect is that the distribution of power on the die (silicon) can vary dynamically depending on the software application that is running. As multi-core, multi-threaded chips become more prominent, these problems are compounded even further. There is another aspect of package cooling analysis which is traditionally ignored, and that is the part-to-part variability in terms of materials and stack up geometry. These can significantly influence the cooling design, and it is important to be aware of their impact. In this study we focus on a stochastic analysis of a hypothetical multi core microprocessor. The power in each block is assumed to a random variable, as are the thickness and conductivities of the die, TIM1, lid (heatspreader), TIM2 and the sink thermal performance. A detailed Monte Carlo analysis of the package coolability is conducted, considering one scenario where power fluctuation is enabled and the other where power is treated as being static. The findings highlight the significance of considering the realistic power fluctuations in the cooling solution design.