A Reconfigurable Digital RF Transceiver in 65nm CMOS
Jiang Feiyu, Liu Fuxiang, Mo Bo, Dang HaonanIntroduction:
The rapid evolution of 4G/5G wireless communication systems and Unmanned Aerial Vehicle (UAV) communication applications has significantly increased the demand for highly integrated and reconfigurable Radio Frequency (RF) transceivers. Conventional RF front-end architectures are typically optimized for fixed frequency bands and communication standards, making them difficult to adapt to multi-band, multi-mode, and wideband communication scenarios. Therefore, developing a fully reconfigurable RF transceiver with high integration, flexible bandwidth configuration, and strong linearity has become an important research topic in modern Software-Defined Radio (SDR) systems.
Methods:
This paper presents a fully reconfigurable digital RF transceiver implemented in a 65 nm CMOS process. The proposed architecture integrates two receive channels, two transmit channels, five fractional-N Phase-Locked Loops (PLLs), and ten high-speed ADC/DAC converters on a single chip with an area smaller than 1 cm². A Zero-IF architecture, combined with tunable RF front-end circuits, including configurable low-pass filters and variable-gain amplifiers, is employed to achieve flexible operation from 300 MHz to 6 GHz. In addition, fourth-order continuous-time Σ-Δ ADCs/DACs with adaptive bandwidth reconfiguration are adopted to support different communication bandwidths ranging from 20 MHz to 100 MHz. To improve system consistency and modulation performance, embedded digital calibration algorithms are introduced for real-time compensation of I/Q imbalance, phase mismatch, and gain drift.
Results:
Measurement results demonstrate that the proposed transceiver achieves excellent RF and communication performance across the target frequency range. The receiver achieves a Noise Figure (NF) lower than 10 dB and an Input third-order Intercept Point (IIP3) greater than 25 dBm at 2.6 GHz. The fourth-order Σ-Δ ADC achieves an SNDR of 70.12 dB and an SFDR of 83.63 dB within a 10 MHz bandwidth. The transmitter achieves an Error Vector Magnitude (EVM) better than −42 dB and an Adjacent Channel Leakage Ratio (ACLR) better than −65 dBc under LTE 20 MHz FDD conditions at 2.6 GHz. The image rejection ratio after digital correction exceeds 65 dB across the operating bandwidth.
Discussion:
Compared with previously reported RF transceiver designs, the proposed architecture demonstrates strong competitiveness in terms of linearity, modulation accuracy, image-rejection capability, and system integration. The combination of reconfigurable analog front-end circuits, adaptive Σ-Δ data converters, and embedded digital correction algorithms significantly enhances the flexibility and robustness of the transceiver under multi-band and multi-standard communication scenarios. Furthermore, the integrated multi-channel architecture effectively reduces system size and implementation complexity while maintaining wideband operation capability.
Conclusion:
A highly integrated and fully reconfigurable digital RF transceiver for SDR applications has been successfully designed and experimentally verified. The proposed transceiver supports dynamic bandwidth configuration from 20 MHz to 100 MHz across a 300 MHz to 6 GHz frequency range, while achieving excellent RF performance and communication quality. The presented architecture provides a practical and flexible hardware platform for future 4G/5G, UAV communication, and multi-standard wireless communication systems.