A Parameter-Reconfigurable FPGA Acceleration Architecture with Unified Multi-Directional Convolution Mapping for UAV Ship Detection

Motivated by the need for low-latency, energy-efficient, and reconfigurable computation in UAV-based maritime monitoring, this paper proposes a parameter-reconfigurable FPGA acceleration architecture that provides a unified mapping for multi-directional convolutions, using the lightweight MPR-ShipNet as the validation network. Through a direction-selection and zero-masking mechanism, the architecture maps horizontal 1 × 3, vertical 3 × 1, and conventional 3 × 3 convolutions onto a shared 3 × 3 processing-element (PE) array. Software instructions dynamically configure convolution, pooling, activation, upsampling, and data-transfer operations, thereby eliminating the need to construct dedicated hardware units for different convolutional operators. The design further incorporates an eight-channel INT8 quantization module, a multichannel pipeline, and on-chip data-reuse mechanisms, which collectively reduce intermediate-feature storage, off-chip memory accesses, and data-transfer overhead. Experimental results show that MPR-ShipNet achieves a precision of 93.7%, a recall of 95.6%, an mAP@0.5 of 94.5%, and an F1-score of 94.6% on the SeaShips dataset. It also maintains robust detection performance under disturbances arising from noise, illumination variation, blur, and occlusion. When implemented on an XC7Z100 FPGA operating at 200 MHz, the proposed accelerator achieves a throughput of 166.35 GOPS, a per-frame inference latency of 74 ms, and a power consumption of 2.59 W, corresponding to an energy efficiency of 64.23 GOPS/W. The INT8-deployed model achieves an mAP@0.5 of 91.5%, representing an absolute decrease of 3.0 percentage points, or a relative decrease of approximately 3.17%, compared with the 94.5% FP32 baseline. These results demonstrate a practical trade-off between detection accuracy and deployment efficiency for resource-constrained edge platforms.