A Low‐Power Two‐Step Gray‐Code Counter Based on Self‐Feedback for SS‐ADC in CMOS Image Sensor

ABSTRACT

This paper presents a low‐power two‐step gray‐code counter based on self‐feedback for single‐slope analog‐to‐digital converter (SS‐ADC) in CMOS image sensor (CIS). The proposed counter implements digital correlated double sampling (D‐CDS) through self‐feedback structure. This structure performs complementary conversion for D‐CDS by feeding the quantized reset voltage state back to the logical feedback DFF (LF‐DFF) directly, reducing the parasitic capacitance and inner flipping nodes. The proposed counter is implemented in an 11‐bit SS‐ADC with 110‐nm CMOS process. Post‐layout simulation results indicate that compared with bitwise‐inversion (BWI) structure, the self‐feedback structure reduces power consumption by 19.5%, whereas the proposed counter achieves 27.4% power savings compared to the two‐step DDR counter. The implemented SS‐ADC consumes 15.3 W each column, with +0.4/0.6 LSB DNL, +0.9/0.5 LSB INL, and 6.4‐s conversion time, delivering a feasible low‐power counting solution for CIS.