A Low‐Overhead SEU‐Resilient and Highly Defect‐Testable Scan‐Test‐Aware Latch Design

ABSTRACT

Sequential elements in nanoscale CMOS circuits are becoming increasingly susceptible to radiation‐induced soft errors. Many hardened latch designs utilize cell‐internal redundancy to achieve soft error tolerance. However, such redundancy masks not only soft errors but also physical defects, thereby degrading test quality. Furthermore, escaped defects may compromise the soft error tolerability of these designs. Existing scan‐test‐aware designs (STAHL and HIDER) use design‐for‐test (DFT) techniques to improve cell‐internal defect detectability and reduce the impact of these potential defects on soft error tolerability. However, these two designs incur higher area and power overheads than existing designs. To overcome the limitations of these two scan‐test‐aware hardened designs, this paper proposes a low‐overhead, highly defect‐detectable, and SEU‐self‐recoverable hardened (LDSH) latch. The LDSH design uses cross‐connection to mitigate the output‐coupling problem of dual‐output C‐element (DOC) and achieve high soft error tolerability. Simulation results demonstrate that, the proposed LDSH achieves the highest defect coverage (DC) of 84.4%, and the lowest post‐test vulnerability factor (PTVF) of 3.37%, indicating that these undetected defects have low impact on the soft error tolerability of the proposed LDSH design. Compared with the two typical scan‐test‐aware latch designs, LDSH reduces power consumption by 72.66%, delay by 85.45%, power‐delay product (PDP) by 96.26%. Furthermore, detailed process, voltage, and temperature (PVT) as well as Monte Carlo simulations verify the low sensitivity of the proposed LDSH latch under the variation of PVT.