A Low-Power JPEG XS Frame Buffer Codec for On-Chip Display Systems

Power consumption in portable display systems is significantly affected by the energy cost of frame buffer memory accesses between the graphics processing unit (GPU) and the display processing unit (DPU). This paper presents the design and FPGA implementation of a visually lossless frame buffer codec based on the JPEG XS standard, intended for integration into on-chip systems to reduce memory bandwidth and associated power consumption. The codec is implemented in VHDL and targets the AMD Artix UltraScale+ xcau15p-2ffvb676e device. The codec supports both the standard ISO/IEC 21122 entropy coding path and a simplified non-standard Golomb–Rice mode intended for closed on-chip systems. Post-place-and-route results at PPC = 4 show that the Standard Precinct codec occupies 22.0% of device LUTs, while the proposed Golomb–Rice variant requires only 15.8%. At a compression ratio of 11:1, the codec achieves a PSNR of 40.20 dB, consistent with visually lossless operation reported for JPEG XS. Power estimation at 200 MHz shows that the Golomb–Rice mode reduces total codec power consumption by 44 mW (4.7%) relative to the Standard Precinct mode, with the decoder contributing the majority of this saving. The proposed solution is applicable to portable devices with built-in displays, including smartphones, tablets, and augmented reality headsets, where tile-based frame buffer compression is required without inter-frame dependencies.