A High-Accuracy Delay-Tap Calibration Method for 100 MHz Time-Mode Signal Processing

In this paper, a calibration technique for unity delay taps suitable for 100 MHz time-mode signal processing is proposed. The delay tap is based on the constant slope discharging capacitor concept which is used in time-mode signal processing building blocks. The proposed topology calibrates the impact of process, voltage supply and temperature variations improving the dynamic range and the accuracy of the delay tap. It contains a digital loop that calibrates the discharging slope. The novelty of this work is that the slope calibration is achieved by adjusting the supply voltage of a driving CMOS inverter avoiding the perturbation of the signal path. All circuits are designed using the 65 nm TSMC technology process, under the nominal supply voltage of 1.2 V. The power consumption of the delay tap is 60 μW for a sampling frequency equal to 100 MHz. The full-scale input range is 2.5 ns. Post-layout simulations show a residual deterministic time error in the range from −18.6 ps to 15.8 ps over 80% of the input full-scale range over process, voltage supply and temperature corners. Monte Carlo mismatch simulations yield a time error standard deviation of approximately 23–25 ps, depending on the input pulse width. The dynamic input range of the delay tap dramatically improves compared to the uncalibrated tap.