A Hardware-Error-Aware Time-Domain CIM Accelerator for AdderNet with Significance-Aware Dual-Mode DTC Encoding and Shared-Clock TDC Readout

Adder neural networks remove multiplication from convolution, yet their direct L1-distance datapath still requires subtraction, absolute-value generation, and wide accumulation. We address this cost by mapping the online L1 operation to minimum selection and time-domain accumulation. The proposed accelerator processes a 3×3×16 window for 16 output channels with 6-bit weights and activations. Each 6-bit minimum is divided into two 3-bit slices. A dual-mode digital-to-time converter (DM-DTC) encodes the most-significant slice in high-linearity (HL) mode and the least-significant slice in low-power (LP) mode. Readout is performed by a shared-clock time-to-digital converter (SC-TDC), in which one Gray-code time reference serves all paths while local latches preserve independent channel results. The training model reproduces code-dependent DTC nonlinearity, process–voltage–temperature variation, jitter, channel offset, TDC quantization, saturation, and scale mismatch. The architecture thereby combines significance-aware time encoding, channel-scalable readout, and hardware-aware adaptation. Post-layout simulations in 55 nm show that the 0.359 mm2, 13.7 Kb design operates at 0.7–1.2 V and 5–30 MHz, consumes 0.025–0.324 mW, and achieves 43.2–94.3 TOPS/W. The normalized figure of merit is 6.01–13.09 POPS/W·bit2. On CIFAR-10/ResNet-20, hardware errors reduce the baseline accuracy from 92.71% to 86.26%; error-aware training achieves 91.53%.