A Direct Fanning-out Packaging Technology using Cu Base Plate for Embedded Fine-pad-pitch LSI

As the wiring of LSI devices continues to shrink, the pitch of the bonding pads becomes smaller and smaller. This makes it more difficult to form connections using flip chip bumps and increases the cost of the interposer substrate. A direct fanning-out packaging technology, named as “SIRRIUS”, gives a solution for this problem. The SIRRIUS package consists of a Cu base plate, a fine-pad-pitch embedded LSI chip, built-up resin layers, and multi-layer fanning-out wiring.

An experiment in which chips with 80-μm-pitch, four rows of pads are embedded clarifies that using a low-viscosity resin and optimizing its thickness are important for achieving fine-pitch interconnects with high reliability. By measuring the displacement of the mounted chips and laser vias, and improving their position accuracy, the feasibility of fabricating the SIRRIUS package with a lump method is demonstrated. A 31-mm-square, 900-pin-count SIRRIUS package with three-layer wiring, 15 μm wide, is successfully fabricated. Its total thickness is only 0.69 mm including the Cu plate. Evaluation of package-level and board-level reliability show no electrical failures or cracks after 600 and 1000 cycles, respectively.

Our “SIRRIUS” package has following features; 1) small package thickness, 2) low cost process due to directly connecting the Cu plating to fine-pitch LSI pads, and 3) high heat dissipation, low package warpage and high reliability, due to the rigid Cu plate. Therefore, the SIRRIUS package is an attractive approach to achieving thin and highly reliable fine-pad-pitch system LSI packages for replacing FCBGA packages.