A Deterministic FPGA-CPU Data Interaction Architecture with Cache-Aware Core Selection for Real-Time Systems

Achieving periodic, low-latency data transfer with deterministic timing guarantees between I/O devices (e.g., Field-Programmable Gate Arrays (FPGAs)) and hosts remains a fundamental challenge in real-time domains, including automated driving, high-frequency trading, and hardware-in-the-loop systems. Unpredictable communication delays or jitter in these applications can directly compromise system correctness and safety. Conventional I/O data interaction mechanisms, which are typically built upon high-speed Network Interface Cards (NICs), USB protocols, and serial interfaces, fall short of meeting these stringent temporal constraints. These generic approaches introduce substantial jitter through heavy protocol overheads (e.g., TCP/UDP processing), mandatory data copies between kernel and user space, and unpredictable packet queuing dynamics, rendering them unsuitable for real-time host–device communication. To address this challenge, we propose a deterministic I/O data interaction architecture that bounds latency jitter through co-optimization across the hardware, driver, operating system, and application layers. The architecture introduces two reusable system-level design principles: interrupt-independent notification via sequence counters, avoiding OS-mediated jitter as much as possible, and cache-aware core selection based on the non-uniform cache architecture (NUCA) to reduce the variability of access latency, thereby achieving a tighter transmission jitter distribution. We systematically evaluate the performance of the proposed architecture under diverse conditions, including different non-uniform memory access (NUMA) nodes and various data direct I/O (DDIO) and cache allocation technology (CAT) configurations. Experimental results show that our approach achieves a peak jitter of approximately 70 ns at 2 µs transmission intervals, which is about 42% lower than the baseline jitter.