A Copper Interconnect Scaling Roadmap for AI and HPC Systems

The performance of modern AI and high-performance computing (HPC) architectures is increasingly constrained by the “memory wall”, the growing disparity between GPU compute speed and HBM memory bandwidth. To sustain performance scaling, interconnect technologies must deliver higher data rates, increased line density, and greater vertical integration without compromising manufacturability or reliability. This work presents a quantitative roadmap for copper interconnect scaling designed to bridge this barrier through coordinated advances in datarate, layer count, and line density (lines-per-millimeter).

We review and project the evolution of copper-based redistribution layer (RDL) architectures beyond today’s CoWoS-class implementations, mapping achievable design points across <2 µm line/space geometries, multi-stack interconnects, and sub-100 µm pitch microbump or hybrid-bonded links. Using published industry data and process simulations, we define the electrical and mechanical scaling limits imposed by resistive, capacitive, and adhesion constraints, and outline pathways to overcome them through new metallization, dielectric, and interface engineering strategies. The resulting roadmap demonstrates that by optimizing copper conductivity, reducing interlayer parasitics, and increasing layer utilization efficiency, aggregate interconnect bandwidth per package area can increase by an order of magnitude while maintaining copper as the enabling material.

The analysis highlights that continued copper scaling – rather than an immediate transition to photonic or exotic interconnects – can extend the life of conventional materials and processes well into the AI-HPC era. By correlating achievable datarates with manufacturable feature sizes and stack heights, this roadmap provides a an accelerated and more efficient pathway toward closing the compute-to-memory performance gap.