DOI: 10.1002/cta.70655 ISSN: 0098-9886

A Circuit‐Theoretic Approach to a Time‐Varying Bilinear Power Converter: Energy‐Passivity and Super‐Twisting Control of the Totem‐Pole Power‐Factor‐Correction Rectifier

Ahmet Çakanel

ABSTRACT

The averaged model of a switched‐mode power converter is a bilinear dynamical circuit; driven by a periodic source, its operating point is a periodic orbit and the stored energy obeys a power‐balance constraint. This paper builds a hierarchical control law directly on that structure for the totem‐pole bridgeless power factor correction (PFC) rectifier: A slow passivity‐based outer loop performs damping injection on the capacitor energy and derives the current amplitude from the power balance, while a fast super‐twisting inner loop drives the inductor current to a time‐varying sliding manifold in finite time (EP‐STA). The stability analysis covers (i) input‐to‐state stability of the energy loop under the periodic power pulsation, with a quantified filter design condition; (ii) finite‐time convergence of the inner loop in its implemented, generalized super‐twisting form with time‐varying gain , with gain conditions the design meets with quantified margins; and (iii) practical stability of the cascade by singular perturbation. The framework is validated on a switching‐level model of a 3.3 kW GaN design including dead time, DCM, sensor noise, quantization, computation delay, and PLL error, yielding a discrete‐time gain rule for delayed super‐twisting implementations and a mode‐aware DCM feedforward. The complete discrete‐time control law is further validated processor‐in‐the‐loop on a 216 MHz Cortex‐M7 microcontroller, reproducing the reference implementation to below one PWM duty LSB and executing within s of the s control period. Against an industrially‐representative PI baseline with identical enhancements, EP‐STA achieves lower distortion (THD 0.5% vs. 1.1% at switching level; 1.6% vs. 1.9% on the averaged model), vs.  start‐up overshoot, and smaller load‐transient excursions, maintaining IEC 61000‐3‐2 Class A compliance from to load. A 1000‐run switching‐level Monte Carlo study () confirms the margins with zero trips. Ablations attribute the transient advantage to the energy outer loop and the robustness under inductance mismatch to the super‐twisting inner loop.