A Capacitorless Graphene Drain Impact Ionization Memory with Ultralow Write Pulses

Abstract

Reducing write voltage directly improves energy efficiency of memories. Here, we demonstrate a capacitorless graphene-drain impact-ionization memory with symmetric ±200 mV write pulses. The device integrates a graphene/silicon heterojunction drain into a silicon-on-insulator transistor, creating a strong drain-side electric field that triggers impact ionization and carrier multiplication to abruptly increase current at the threshold voltage. Thus, the device achieves subthreshold swings of 0.29 and 0.25 mV/dec for the forward and backward sweeps, respectively. Meanwhile, floating-body charge storage creates a stable ∼0.2 V hysteresis window, enabling state switching with a 200 mV (>1/2 hysteresis window) gate-voltage excursion. These characteristics enable capacitorless memory operation with record-low write-pulse voltages. A 200 mV/10 ns pulse writes the ‘1’ state and produces a 3.2 decade current-state margin, whereas a −200 mV/10 ns pulse writes the ‘0’ state and produces a 3.9 decade current-state margin. Leveraging these attributes, a 1T low-swing pulse encryption scheme is further demonstrated for low-power encoding of pulse sequences.