A Capacitor-Less Low Dropout Regulator with Wide Input Range and High Power-Supply Rejection Ratio

This paper presents a capacitor-less low-dropout regulator (LDO) with a wide input-voltage range and high power-supply rejection ratio (PSRR), designed and laid out in a 0.18 μm CMOS process. The design incorporates a pre-regulation circuit to suppress power-supply noise. The proposed LDO supports an input-voltage range from 3.3 V to 40 V while maintaining an output voltage of 3.3 V. The integrated output noise from 10 Hz to 100 kHz is 4.3 nV2. The proposed LDO achieves a PSRR of −109 dB at 1 kHz under a maximum load current of 100 mA, representing a 20 dB improvement compared with the same LDO without the pre-regulation circuit.